1. Field of the Invention
The present invention relates to a D/A converting system for digital-to-analog converting a signal modulated by a delta sigma modulator, and in particular relates to a delta sigma modulation D/A converting system including a plurality of D/A converters.
2. Prior Art
Conventionally, a delta sigma modulation D/A converting system has been known as a high resolution D/A converting system, and such a delta sigma modulation D/A converting system has been used in digital audio equipment or the like.
FIG. 6 is a block diagram showing a configuration of a prior-art delta sigma modulation D/A converting system.
A digital signal is inputted to a delta sigma modulator 51 and is modulated into a PDM (Pulse Density Modulation) signal in which data of more than ten bits is bit-compressed to several bits. The PDM signal is then inputted to a D/A converter 52 and is outputted therefrom as an analog signal. Furthermore, a clock generator 73 supplies a clock CK1 and a clock CK 2 to the delta sigma modulator 51 and the D/A converter 52, respectively.
As a configuration example of the delta sigma modulator 51, a block diagram of a cascade delta sigma modulator is shown in FIG. 7. The cascade delta sigma modulator includes: a main loop 1 and a sub-loop 2 operated at a sampling frequency determined by the clock CK1 supplied from the clock generator 73; and a noise removal section 3. The sampling frequency is normally set sufficiently higher than the frequency of a digital input signal (i.e., set at about 16 to about 64 times as much as the frequency of a digital input signal).
The main loop 1 includes an adder 4, a local quantizer 5, a subtractor 6, and a delay device 7. A digital signal X is added to a feedback signal sent via the delay device 7 by the adder 4, and is bit-compressed to a predetermined level by the local quantizer 5. If a quantization error, which occurs due to the bit compression of the local quantizer 5, is defined as Q1, an output of the subtractor 6 becomes −Q1, and a transfer function of an output Y1 from the main loop 1 is expressed as the following equation:Y1=X+(1−Z−1)·Q1  (1)
On the other hand, the sub-loop 2 includes an adder 8, a local quantizer 9, a subtractor 10, and an integrator 11. A signal inputted to the sub-loop 2 (=−Q1) is added to a feedback signal returned via the integrator 11 by the adder 8, and is bit-compressed to a predetermined level by the local quantizer 9. If a quantization error, which occurs due to the bit compression of the local quantizer 9, is defined as Q2, an output of the subtractor 10 becomes −Q2. Accordingly, if a transfer function of the integrator 11 is defined as H (Z), a transfer function of an output Y2 from the sub-loop 2 is expressed as the following equation:Y2=−Q1+(1−H(Z))·Q2
The output Y2 from the sub-loop 2 is differentiated by a differentiator 13 in the noise removal section 3, and is added to the output Y1 of the main loop 1 by an adder 12. Accordingly, a final output Y of the delta sigma modulator is expressed as the following equation:
                                                        Y              =                                                Y                  ⁢                                                                          ⁢                  1                                +                                                                            (                                              1                        -                                                  Z                                                      -                            1                                                                                              )                                        ·                    Y                                    ⁢                                                                          ⁢                  2                                                                                                        =                              X                +                                                                            (                                              1                        -                                                  Z                                                      -                            1                                                                                              )                                        ·                                          (                                              1                        -                                                  H                          ⁡                                                      (                            Z                            )                                                                                              )                                        ·                    Q                                    ⁢                                                                          ⁢                  2                                                                                        (        2        )            
If the number of quantization levels of the local quantizer 5 is 7-value while the number of quantization levels of the local quantizer 9 is 3-value, for example, the local quantizers 5 and 9 carry out quantization as shown in Table 1 and Table 2. It should be noted that the output is standardized at 16384.
TABLE 1InputOutput 28160 or more+3 16896 to 28159+2 5632 to 16895+1 −5632 to 56310−16896 to −5633−1−28160 to −16897−2−28161 or less−3
TABLE 2InputOutput 5632 or more+1−5632 to 56320−5633 or less−1
If the numbers of quantization levels of the local quantizers 5 and 9 are defined as L1 and L2, respectively, while a quantization noise per unit of quantization level of the local quantizer 9 is defined as E2, then the quantization error Q2 of the local quantizer 9 can be expressed as follows: Q2=E2/(L1+L2). Therefore, if this equation is substituted into Equation (2), the output Y of the delta sigma modulator is expressed as the following equation:Y=X+(1−Z−1)·(1−H(Z))·E2/(L1+L2)  (3)
Next, a specific configuration of the integrator 11 will be described below. FIG. 8 is a block diagram of the integrator 11. An input (−Q2) is supplied to a delay circuit 21, and is shifted to delay circuits 22 through 24 in sequence. Outputs of the delay circuits 21 through 24 are multiplied k1-fold, k2-fold, k3-fold and k4-fold by multipliers 29 through 32, respectively, while outputs of delay circuits 25 through 28 are multiplied a-fold, b-fold, c-fold and d-fold by multipliers 33 through 36, respectively. Then, adders 37 through 43 add the outputs of the delay circuits 21 through 24 to the outputs of the delay circuits 25 through 28, and output the resulting values, which are to be inputted to the delay circuit 25.
Therefore, a transfer function H (Z) of the integrator 11 is expressed as the following equation:H(Z)=(k1·Z−1+k2·Z−2+k3·Z−3+k4·Z−4)/(1+a·Z−1+b·Z−2+c·Z−3+d·Z−4)  (4)If Equation (4) is substituted into Equation (3), the output Y of the delta sigma modulator is expressed as the following equation:Y=X+(1−Z−1)·(1+(a−k1)·Z−1+(b−k2)·Z−2+(C−k3)·Z−3+(d−k4)·Z−4)/((1+a·Z−1+b·Z−2+c·Z−3+d·Z−4)·E2/(L1+L2)  (5)Furthermore, it can be seen from Equations (4) and (5) that the order of the integrator 11, i.e., the order of a transfer function of the delta sigma modulator, is determined by the values of factors k1, k2, k3, k4, a, b, c, and d of the multipliers 29 through 36.
Table 3 shows exemplary settings for the factors of the integrator 11 and the order of a transfer function of the delta sigma modulator. Furthermore, the transfer function of the delta sigma modulator in the case where each factor is substituted into the integrator 11 is expressed as Equations (6) through (8) as follows:Y=X+(1−Z−1)3.E2/(L1+L2)  (6)Y=X+(1−Z−1)4/(1−Z−1+0.5Z−2).E2/(L1+L2)  (7)Y=X+(1−Z−1)5/(1−2Z−1+2Z−2).E2/(L1+L2)  (8)
TABLE 3DeltaFactorSigmaEqabcdk1k2k3K4Order(6)00002−1003(7)−10.5002−2.5104(8)−22002−44−15
Now, consideration will be given to a dynamic range of a delta sigma modulator. The dynamic range is expressed as a ratio between a maximum amplitude of an input signal X and a quantization noise level. For example, if the maximum amplitude of the input signal X is defined as Xmax in the case of Equation (6), the dynamic range is expressed as the following equation:Dynamic range=Xmax/{(1−Z−1)3·E2/(L1+L2)}  (9)
Based on this result, it can be seen that the higher the numbers of quantization levels (L1, L2) of the local quantizers 5 and 9 and the order of the integrator 11, the more likely it is that a high dynamic range can be realized. However, the delta sigma modulator forms a feedback loop; therefore, if a large amplitude is inputted in the loop, there arises the problem that it becomes impossible to catch up with the feedback, resulting in unfavorable oscillation. In addition, the higher the order of the transfer function, the slower the response of a feedback signal to the input signal, thus making it more likely to cause the oscillation. Accordingly, even if the order of the transfer function is excessively increased in order to increase the dynamic range, the allowable input amplitude is limited, thus conversely reducing the dynamic range.
To cope with these problems, in a high-order delta sigma modulator, a method for increasing the number of levels of a quantizer to raise the speed of a feedback response is used.
Further, as a means of increasing the dynamic range (D-range) of the delta sigma modulator, a method for increasing the sampling frequency to raise the over-sampling rate (OSR) with respect to the frequency of the input signal X is also used.
Next, in giving consideration to a delta sigma modulator used in a delta sigma modulation D/A converting system, a percentage modulation is an important item. The percentage modulation represents a ratio between a maximum amplitude of an output Y and a maximum amplitude of an input signal X. As a specific example, consideration will be given to the percentage modulation of the cascade delta sigma modulator shown in FIG. 7. If the number of quantization levels of the local quantizer 5 in the main loop 1 is defined as L1, and the number of quantization levels of the quantizer 9 in the sub-loop 2 is defined as L2, then the maximum amplitude of the output Y1 and the maximum amplitude of the output Y2 are represented by L1 and L2, respectively. Furthermore, L2 is expressed as 2(L2−1) after having passed through the differentiator 13. Accordingly, a maximum amplitude Ymax of the output Y is expressed as the following equation:Ymax=(L1−1)+2(L2−1)  (10)In this case, the maximum amplitude Xmax of the input signal X is expressed as the following equation:Xmax=L1−1  (11)
Therefore, the percentage modulation is expressed as follows:
                                                                        Percentage                ⁢                                                                  ⁢                modulation                            =                              X                ⁢                                                                  ⁢                                  max                  /                  Y                                ⁢                                                                  ⁢                max                                                                                        =                                                                    (                                                                  L                        ⁢                                                                                                  ⁢                        1                                            -                      1                                        )                                    /                                      (                                                                  L                        ⁢                                                                                                  ⁢                        1                                            -                      1                                        )                                                  +                                  2                  ⁢                                      (                                                                  L                        ⁢                                                                                                  ⁢                        2                                            -                      1                                        )                                                                                                                          =                                                (                                                            L                      ⁢                                                                                          ⁢                      1                                        -                    1                                    )                                /                                  (                                                            L                      ⁢                                                                                          ⁢                      1                                        +                                          2                      ⁢                      L                      ⁢                                                                                          ⁢                      2                                        -                    3                                    )                                                                                        (        12        )            
As a result, if L1=9-value and L2=3-value, then the percentage modulation=0.67. Further, it can be seen that, in the delta sigma modulator shown in FIG. 7, the smaller the number L1 of quantization levels of the local quantizer 5 in the main loop 1, the lower the percentage modulation.
Comparative results showing the relationships among the number of quantization levels, OSR, percentage modulation and D-range are exemplarily shown in Table 4 below. In this example, a fourth-order delta sigma modulator is used, and the final output level L(=L1+2L2−2) of the delta sigma modulator is also shown in Table 4.
TABLE 4QuantizationPercentageLevelOSR [-fold]Modulation [%]D-range [dB]L1 = 5 − value165085L2 = 3 − value32113 L = 7 − value64140L1 = 7 − value166088L2 = 3 − value32115 L = 9 − value64142L1 = 9 − value166790L2 = 3 − value32117 L = 13 − value64144
Next, a configuration of the D/A converter 52 used in the delta sigma modulation D/A converting system will be described with reference to FIG. 9. The D/A converter 52 includes: a PWM (Pulse Width Modulation) section 521 operated at a frequency determined by the clock CK2 supplied from the clock generator 73; and an amplifier section 522. A multi-valued PDM signal outputted from the delta sigma modulator is converted into a binary PWM signal by the PWM section 521, and is inputted to the amplifier section 522.
The amplifier section 522 includes an amplifier 523 and an LPF (low-pass filter) 524. The PWM signal inputted to the amplifier section 522 is amplified by the amplifier 523, has its high-frequency component removed by the LPF 524, and is outputted as an analog signal.
FIG. 10 shows the relationship between the PDM signal and the output of the PWM signal in the case where a 7-value PDM signal is inputted to the PWM section 521. The 7-value PDM signal is developed along the time axis at a clock frequency six times as much as the sampling frequency of the delta sigma modulator, and is converted into a binary signal. In other words, the clock frequency of the PWM signal is determined by the product of the sampling frequency and the number of quantization levels of the delta sigma modulator.
The amplifier section 522 used in a D/A converter can be classified into several types depending on a configuration of an output stage thereof, as typified by a linear amplifier and a digital amplifier. As a linear amplifier, a class A amplifier, a class B amplifier or a class AB amplifier is well known, and a digital amplifier is also called a “class D amplifier”. A linear amplifier is advantageous in that the output amplitude can be increased, but is disadvantageous in that the thermal efficiency is unfavorably low. On the other hand, a digital amplifier is advantageous in that the thermal efficiency is high, but is disadvantageous in that the output amplitude is unfavorably reduced since the output amplitude is limited by the percentage modulation.
FIG. 11 shows a configuration of a class AB linear amplifier. A PWM signal, first, has its high-frequency component removed by an LPF 524, and is inputted to an amplifier 523. The signal inputted to the amplifier 523 is amplified and converted into a differential signal at a drive stage 611, and then drives an output transistor of a class AB output stage 612.
To the contrary, in a digital amplifier shown in FIG. 12, a PWM signal is, first, inputted to a drive stage 613 of an amplifier 523, and then drives an output transistor of a class D output stage 614. Thereafter, the signal has its high-frequency component removed by an LPF 524 consisting of a low-loss LC filter.
In the class AB amplifier, it is necessary to flow a bias current through the output stage so as not to cause distortion. On the other hand, in the class D amplifier, although an electric current momentarily flows through the output transistor when it is switched from ON to OFF or from OFF to ON, no electric current flows therethrough after the transistor has been switched to ON or OFF; therefore, the loss (heat generation) at the output stage is low, thus making it possible to realize a high efficiency.
Furthermore, in the class D amplifier, the PWM signal is outputted as it is, and therefore, the maximum output amplitude of an analog signal is determined by the percentage modulation of the output stage. Accordingly, when the output power is desired to be increased, it is necessary to increase the number of quantization levels of the delta sigma modulator, and to raise the percentage modulation. However, as already described with reference to FIG. 10, the clock frequency of the PWM signal is determined by the product of the sampling frequency and the number of quantization levels of the delta sigma modulator, and therefore, the clock frequency of the PWM signal is raised if the number of quantization levels is increased. If the clock frequency of the PWM signal is raised, it becomes susceptible to clock jitter or waveform rounding, which appears as waveform distortion or noise after having been converted into an analog signal. In general, the clock frequency of the PWM signal is preferably set at 10 MHz or less; therefore, to cope with the above-mentioned problem, it is necessary to decrease the sampling frequency in accordance with an increase in the number of quantization levels of the delta sigma modulator.
In the case where the class AB amplifier is used, as a configuration of a D/A converter, a switched capacitor D/A converter may be used as shown in FIG. 13. The switched capacitor D/A converter includes: capacitative elements C1 through Cn; switches SW1 through SW4 and SW11 through SW1n; an operational amplifier 525; and a clock generator 526. Furthermore, the clock generator 526 generates a clock Φ1, and a clock Φ2 that has been inverted from the clock Φ1 by an inverter 527. A PDM signal outputted from the delta sigma modulator is supplied to the switches SW11 through SW1n, and the number (=n) of the switches is equal to the number of levels of the PDM signal.
The switches SW1 and SW4 each enter a closed state when the clock Φ1 is at a high level, and enter an open state when the clock Φ1 is at a low level. Further, when digital data of respective levels of the PDM signal are defined as S1 through Sn, the switches SW11 through SW1n are connected to any of reference voltage sources (Vr+, Vr−) in accordance with the polarities (high or low) of the data S1 through Sn. Furthermore, the reference characters S1b through Snb represent inversion signals of the data S1 through Sn.
Accordingly, when the clock Φ1 is at a high level (i.e., when the clock Φ2 is at a low level), the left sides of the capacitative elements C1 through Cn are connected to the reference voltage sources Vr+ or Vr− in accordance with the polarities of the digital data S1 through Sn, while the right sides of the capacitative elements C1 through Cn are connected to reference voltage sources Vro, thus allowing electric charges to be stored in the capacitative elements C1 through Cn. In this case, since the switch SW4 is also in a closed state, both ends of a capacitor Cout are short-circuited, and electric charges stored in the capacitor Cout are discharged.
Next, when the clock Φ2 is at a high level (i.e., when the clock Φ1 is at a low level), the switches SW2 and SW3 each enter a closed state while the switches SW1 and SW4 each enter an open state. In this case, the left sides of the capacitative elements C1 through Cn are connected to the reference voltage sources Vro while the right sides of the capacitative elements C1 through Cn are also each connected to the reference voltage source Vro since it serves as a virtual ground point of the operational amplifier 525. Thus, due to charge conservation, the electric charges stored in the capacitative elements C1 through Cn are transferred to the capacitor Cout, and are presented as an output Vout of the operational amplifier 525. If the following equation: Vr+−Vro=Vro−Vr−=Vr is true, the output Vout of this switched capacitor D/A converter is expressed as the following equation:Vout={Vr·(S1·C1+S2·C2+ . . . +Sn·Cn)−Vr·(S1b·C1+S2b·C2+ . . . +Snb·Cn)}/Cout  (13)
The clock Φ2, Φ2 (CK2) supplied to the switched capacitor D/A converter is normally used as a value equivalent to the sampling frequency of the delta sigma modulator. Therefore, unlike the configuration using PWM, the switched capacitor D/A converter has an advantage that it is unnecessary to decrease the sampling frequency even if the number of quantization levels of the delta sigma modulator is increased.
A D/A converting system intended for digital audio equipment, in particular portable equipment, is often required to output two types of analog audio signals to two terminals, i.e., a line terminal and a headphone terminal, and in such a case, this system is configured as shown in FIG. 14. A digital signal is inputted to a delta sigma modulator 51, and is modulated into a PDM signal. The PDM signal is inputted to D/A converters 61 and 62, and outputted therefrom as a first analog signal and a second analog signal. The first and second analog signals are connected to a line terminal and a headphone terminal, respectively. For an output to the headphone terminal, a relatively high power of about 40 mW is required at a load of 16Ω, and therefore, a digital amplifier with a high thermal efficiency is suitable as an amplifier section of the D/A converter 62. On the other hand, for an output to the line terminal, a high dynamic range is required; however, the output power is as low as 1 mW or less, which makes the efficiency negligible, and therefore, a linear amplifier capable of increasing the output amplitude is suitable as an amplifier section of the D/A converter 61. Accordingly, a linear amplifier is preferably used in the amplifier section of the D/A converter 61 in FIG. 14, while a digital amplifier is preferably used in the amplifier section of the D/A converter 62 in FIG. 14.
The problem in this case is that the specifications of a linear amplifier and a digital amplifier required for the delta sigma modulator are different. In a digital amplifier, the percentage modulation of the delta sigma modulator has to be increased as much as possible as already described above. To the contrary, in a linear amplifier, the percentage modulation is negligible because the output signal amplitude can be adjusted at a drive stage; whereas, in the case of the use for a line terminal, a dynamic range of 16-bit accuracy (i.e., 98 dB) or more is required.
However, in the conventional delta sigma modulation D/A converting system shown in FIG. 14, only one delta sigma modulator is used; therefore, for example, the description will be made with reference to Table 4 shown above as follows. If the number of quantization levels is set at 13-value in order to make the delta sigma modulator suitable for a digital amplifier, the percentage modulation is 67%, and thus the output power for the headphone terminal is about 40 mW (at a load of 16Ω and a supply voltage of 3.3V). In this case, if an attempt is made to set the clock frequency of the PWM signal at 10 MHz or less while the number of quantization levels is 13-value, the sampling frequency of the delta sigma modulator has to be set at 770 kHz or less. Since a digital signal is inputted at 44.1 kHz, the allowable over-sampling rate is 16 times or less. Therefore, the theoretical value of the dynamic range of the delta sigma modulator is merely 90 dB, which cannot satisfy the performance requirements of the line terminal.
A method for increasing the dynamic range by increasing the order of a transfer function of the delta sigma modulator may be used; however, as already mentioned above, if the order of the transfer function is excessively increased, oscillation is likely to occur when a large amplitude is inputted, which conversely reduces the dynamic range.
On the other hand, if the over-sampling rate is set at 32 times in order to make the delta sigma modulator suitable for a linear amplifier, the number of quantization levels allowable by the clock frequency of the PWM signal is 7-value or less, and thus the percentage modulation is 50%. If the resultant PDM signal is used for a headphone terminal as an output of a class D amplifier, an output power of merely about 20 mW is achieved.
To cope with these problems, one delta sigma modulator may be provided exclusively to one D/A converter in which a class AB amplifier is used, while another delta sigma modulator may be provided exclusively to another D/A converter in which a class D amplifier is used. However, in such a case, there arises a new problem that the power consumption and circuit size are nearly doubled.